For graphics/multimedia applications, video data (i.e., audio and visual data) may be captured by a chipset from a video source using general video capturing techniques. The captured video data is presented for display on a display monitor. During active video re-animation, a series of images may be displayed on a display monitor in sequential order. Video data may be sequentially stored in a pair of buffers. Software is typically provided to drive video hardware specifically configured to sequentially store images in those buffers and “flip” display contents from one image to another. The way to control the switch from one buffer to another is called a buffer flip. The flipping of display contents of images may be activated through a software interrupt service provided by an operating systems (OS) such as Microsoft Windows™.
The flip may be synchronized to the display Vertical Synchronization (VSYNC) signal or not. As non-synchronized flip may cause tearing artifacts, most flips are synchronized to the display VSYNC. Delays and drops of the content in a video frame buffer may happen from time to time as shown in FIG. 1. The drops and delays cause jitter and other visual defects on images presented on the display monitor. The top time line of the graph marks the flip commands and their associated instruction pointers. The bottom time line marks the occurrence of each display VSYNC pulse. Arrow points to the VSYNC for a given flip. FIG. 2 indicates a frame buffer flip register with corresponding entries to the timeline of FIG. 1.
Every time a buffer flip command (also known as a buffer flip instruction) comes in from the software, the associated instruction pointer is stored as an entry in the frame buffer flip queue. Generally, each time a VSYNC pulse occurs the instruction pointer entries in the frame buffer flip queue advance causing an entry lower in depth to overwrite the top entry in depth. The instruction pointer indicates the location for the video data to be displayed on the video monitor changes as well as the particular frame buffer that stores the rendered video data.
However, as FIG. 1 indicates between times T4 through T7, delays in displaying the content in a buffer of the frame buffer may occur to cause defects in the presented video display. The flip command with an associated instruction pointer number 2 (Ptr 2) is loaded into the frame buffer flip queue just after the VSYNC pulse at time T5. The rendered video data displayed at T4 does not change until two VSYNC pulses later at T7.
Moreover, as FIG. 1 indicates between times T7 through T10, the content in a buffer of the frame buffer may be dropped entirely and not presented on the display monitor. The flip command with an associated instruction pointer number 3 (Ptr 3) is loaded into the frame buffer flip queue just after the VSYNC pulse at time T7. The flip command with an associated instruction pointer number 4 (Ptr 4) is loaded into the frame buffer flip queue after the VSYNC pulse at time T7 and before the next successive VSYNC pulse at time T10. The content in a buffer of the frame buffer associated with Ptr 3 is dropped/overwritten without being presented on the display monitor.
Note, in a previous implementation the video graphics display process, the software or hardware typically poll to see if a flip is complete. If flip delay or frame drop occurs with software polling, that may also mean significant CPU cycles spent from that point forward to synchronize the video display process. Also, the frame buffer flip queue may differ from a register storing one entry and possibly a status flag.
While the invention is subject to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. The embodiments of the invention should be understood to not be limited to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.